1. Field
Generally, the present disclosure relates to Memory Built-In Self-Test (MBIST) for semiconductor devices, and, more specifically, to a MBIST architecture for testing on-board cache and other memory arrays in, e.g., a multicore processor.
2. Description of the Related Art
Modern day microprocessors come with many different types of on-chip memory. Examples include cache, tag, least recently used (LRU), and various types of queues, such as centralized run, data, and core request queues (CRQ). Other semiconductor devices have other memory needs. As the size of semiconductor structures continues to shrink, more and greater-sized memory arrays can be placed on a single chip. More memory arrays means more Memory Built-In Self-Test (MBIST) testing, longer power-up times to allow for memory testing to complete, and greater power draw.
Power draw is an important consideration when designing portable, battery-powered devices like smart phones, tablet PCs, personal digital assistants (PDAs), pocket computers, and music players. These devices typically include one or more microprocessors that undergo MBIST testing upon power-up or during a wake-up cycle. When testing multiple memory arrays simultaneously (i.e., in parallel) more transistors are cycled at once than when the memory arrays are tested in serial. Testing each memory array in serial reduces overall power draw.
Testing each memory array in serial, however, increases the amount of time it takes for a device to complete power-up self-tests or recover from a sleep state. Furthermore, devices having more or larger sized memory arrays take more time to test than devices having fewer or smaller-sized memory arrays. Longer power-up or wake-up time is undesirable unless there is some benefit that can be obtained, like conserving battery life.
Scalability is also a consideration. Structures that perform MBIST testing are typically designed to the particular memories they test. Adding additional or different types of memory to a microprocessor, e.g., or resizing existing arrays usually means adding more logic to control testing.
Timing constraints also impose restrictions. Built-In Self-Test (BIST) timing typically requires memory test circuits to be placed in proximity to BIST controllers. Devices having a greater number of memory arrays spread over the same size (or wider) chip area may run into timing problems and additional routing complexities.